This invention relates to a non-volatile semiconductor memory device, and more particularly to a NOR-type flash memory having a function for controlling the range of distribution of the threshold voltages of memory cells obtained after data erasion.
In NOR-type flash memory devices, reduction of the voltage of a power supply and increase of reading speed are demanded. To realize this simultaneously, it is important to minimize the range of distribution of the threshold values of memory cells in an erased state (this distribution will be hereinafter referred to as an xe2x80x9cerasion distributionxe2x80x9d).
To execute each-bit verification and weak programming after erasion are considered as means for reducing the range of distribution of memory cell thresholds (hereinafter referred to as xe2x80x9ccell thresholdsxe2x80x9d) in a NOR-type flash memory.
The each-bit verification indicates verification executed in units of one bit, and the weak programming is programming of a smaller amount than usual. In the weak programming, a smaller amount of bias current than in usual programming is applied to a memory cell gate or drain to thereby minimize the range of changes in threshold value.
The weak programming operation of the NOR-type flash memory will be described.
FIG. 1A shows a distribution of cell thresholds of a memory cell array after erasion. FIG. 1B shows a distribution of cell thresholds of a memory cell array after weak programming.
As is shown in FIG. 1A, erasion reduces the cell threshold values Vth to values lower than an erase verify level EV. After erasion, weak programming is executed on cells having threshold values Vth lower than an over erase verify level OEV. As a result, as is shown in FIG. 1B, the cell threshold values Vth fall within a range of from the erasion verify level EV to the over erase verify level OEV. In other words, the distribution of the cell threshold values is reduced to the range of OEV less than Vth less than EV.
FIG. 2 illustrates a sequence of processing for realizing a distribution range of cell threshold values Vth as shown in FIG. 1B. FIG. 2 is a flowchart useful in explaining a conventional each-bit verifying operation and weak programming operation.
First, an erasion operation is performed until the upper limit of the distribution of the cell threshold values Vth reaches the erasion verify level EV. Subsequently, to raise the lower limit of the erasion distribution of the cell threshold values Vth up to the over erase verify level OEV, each-bit verification and weak programming are performed. In the each-bit verification, the gate voltage Vg of each cell is set at OEV, all cells are sequentially subjected to verification.
If the verification result for each of cells corresponding to an address to be verified is OK (Vthxe2x89xa7OEV), this address is counted up, and each of cells corresponding to the next address is accessed. On the other hand, if the verification result is NG (Vth less than OEV), each cell is subjected to weak programming. This verification and weak programming is repeated until the threshold value Vth of each cell exceeds OEV. After that, it is determined whether or not the verification results of all cells are OK, thereby finishing the sequence of processing.
In the weak programming, the gate voltage Vg and the drain voltage Vd of each cell and the period of programming are set so that the cell threshold value Vth will not exceed the erase verify level EV.
The period required for erasing a memory chip is defined as a period that includes a period required for cell erasion and also required for verification of each bit and weak programming to reduce the range of distribution of cell threshold values. Accordingly, the verification of each bit and weak programming must be executed within as short a period as possible, and it is desirable that the period of voltage application to each cell during weak programming should be as short (for example, 1.5 xcexcsec.) as in usual programming.
The relationship between a period required for hot electron writing and a change in the threshold value of a memory cell in the NOR-type flash memory is usually as shown in FIG. 3. FIG. 3 shows cell writing characteristics, the ordinate and the abscissa indicating a change xcex94Vth (V) in the cell threshold value Vth and a writing time period (xcexcsec.) (logarithm), respectively. In the case of FIG. 3, the drain voltage of each cell is fixed at 5V, and the gate voltage vg applied when writing is used as a parameter.
The writing characteristics change from a linear area (xe2x89xa610 xcexcsec.) in which the cell threshold value Vth increases as the writing time period increases, to a saturated area in which the degree of an increase in the cell threshold value Vth gradually reduces.
Since the above-mentioned weak programming is executed using a short pulse of 10 xcexcsec. or less, it has the writing characteristics of the linear area. In the writing characteristics of the linear area, a change xcex94Vth in the cell threshold value Vth is greatly influenced by variations in memory cells or the temperature. In particular, the change xcex94Vth greatly depends upon the temperature.
FIG. 4 shows the dependency, upon the temperature, of a writing time period required for shifting the cell threshold value Vth from 0V to 2V in the linear area of the writing characteristics shown in FIG. 3.
It is understood from the temperature dependency that where the gate voltage Vg is fixed when writing, the time required for shifting the cell threshold value Vth by 2V at 100xc2x0 C. and xe2x88x9240xc2x0 C. differs by a maximum multiple of ten.
The execution, under these circumstances, of the each-bit verification and the weak programming shown in FIG. 2 will be described.
Since the cell threshold value Vth must not exceed the erase verify level EV even after weak programming, it is necessary to set the gate voltage Vg applied when weak programming so that the cell threshold value will not exceed the erase verify level EV at a low temperature at which the writing speed is high. This setting, however, may create a case where the time required for weak programming will be, at maximum, ten times greater at a high temperature at which the writing speed is low, than at a low temperature at which the writing speed is high.
Further, the time required for each-bit verification and weak programming after data erasion varies depending upon variations between memory chips or blocks. The block is an aggregate of memory cells which can be erased simultaneously, and a minimum unit assumed when executing erasion.
In the above-described conventional non-volatile semiconductor memory, the time required for shifting the cell threshold value greatly depends upon the temperature when executing each-bit verification and weak programming after data erasion. Accordingly, the time required for each-bit verification and weak programming will inevitably be much longer at a high temperature at which the writing speed is low.
The present invention has been developed to solve the above problem, and aims to provide a non-volatile semiconductor memory device in which, when sequentially selecting memory cells from a memory cell array to write data therein, the time required for the writing can be minimized at any optional temperature that falls within an operation-guaranteed temperature range.
To attain the aim, there is provided a non-volatile semiconductor memory device comprising: a memory cell array having a plurality of non-volatile memory cells; and a control section for controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasion of data from the selected memory, wherein the control section changes addresses for designating memory cells in the memory cell array to sequentially selects them, the control section executing writing on memory cells under a first writing condition until a predetermined address is reached, and executing writing on memory cells under a second writing condition after the predetermined address.
When the non-volatile semiconductor memory device constructed as above sequentially selects a plurality of memory cells in a memory cell array to write data therein, it can minimize the time required for writing at any optional temperature within an operation guaranteed temperature range by changing the writing condition in different address zones of the memory cells.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
FIG. 1A is a graph showing a distribution of cell threshold values after an erasion operation is executed in a memory cell array of a flash memory;
FIG. 1B is a graph showing a distribution of the cell threshold values after weak programming is executed in the memory cell array;
FIG. 2 is a flowchart useful in explaining the conventional operations of each-bit verification and weak programming;
FIG. 3 is a graph illustrating the relationship between a hot electron writing period in a flash memory and a change in a cell threshold value;
FIG. 4 is a view showing the dependency, upon temperature, of the writing time required for shifting the cell threshold value by 2V in a linear area of writing characteristics shown in FIG. 3;
FIG. 5 is a schematic block diagram showing a NOR-type flash memory (memory chip) according to a first embodiment of the invention;
FIG. 6 is a conceptual view showing the states of first and second groups in an address space incorporated in the NOR-type flash memory;
FIG. 7A is a circuit diagram illustrating a weak programming controller in the flash memory of FIG. 5;
FIG. 7B is a circuit diagram illustrating a divider circuit as a first-stage divider circuit of the weak programming controller;
FIG. 8A is a circuit diagram illustrating a D/A converter used as an example of a regulator in the flash memory of FIG. 5;
FIG. 8B is a circuit diagram showing a voltage switching circuit used as another example of the regulator;
FIG. 9 is a flowchart useful in explaining each-bit verification and weak programming performed in the flash memory of FIG. 5;
FIG. 10 is a graph showing a distribution of cell threshold values after erasion;
FIG. 11 is a table showing examples of verification results obtained when three memory cells are simultaneously selected;
FIG. 12 is a conceptual view showing the state of a first group in another address space employed in the NOR-type flash memory;
FIG. 13 is a block diagram illustrating the structures of a weak programming controller and a regulator employed in a second embodiment of the invention;
FIG. 14 is a circuit diagram showing the structure of a D/A converter appearing in FIG. 13;
FIG. 15 is a block diagram illustrating the structures of a weak programming controller and a regulator employed in a third embodiment of the invention;
FIG. 16 is a table showing the relationship between the input and output of a D/A converter appearing in FIG. 15;
FIGS. 17A and 17B are circuit diagrams showing an adder incorporated in the weak programming controller shown in FIG. 15;
FIG. 18 is a table illustrating the relationship between an input signal IN2 input to the adder incorporated in the weak programming controller and regulator shown in FIG. 15, and an increase in gate voltage Vg;
FIG. 19A is a circuit diagram showing the structure of an address controller incorporated in a fourth embodiment of the invention;
FIG. 19B is a circuit diagram showing the structure of an address counter incorporated in the address controller;
FIG. 20 is a timing chart indicating the operation of the address controller of FIG. 19A;
FIG. 21 is a circuit diagram showing a SEND signal generating circuit incorporated in the address controller of FIG. 19B;
FIG. 22 is a circuit diagram showing a SEND signal generating circuit corresponding to multi-block-simultaneous-erasion in the address controller of FIG. 19B;
FIGS. 23A and 23B are conceptual views illustrating cell arrays used as samples when performing multi-block simultaneous erasion on regular blocks in the third embodiment of the invention;
FIG. 23C is a conceptual view showing an example of a cell array used as a sample when performing multi-block simultaneous erasion on irregular blocks;
FIG. 24 is a schematic view showing an example of a relationship between each signal and each address obtained by executing sample writing after the restoration from an erasion suspend mode in a fifth embodiment of the invention;
FIG. 25 is a circuit diagram showing a weak programming controller and a SEND signal generating circuit incorporated in the fifth embodiment of the invention;
FIG. 26 is a flowchart useful in explaining each-bit verification and weak programming performed in a seventh embodiment of the invention;
FIG. 27 is a view showing changes in gate voltage Vg in the weak programming performed in the seventh embodiment of the invention;
FIGS. 28A and 28B are circuit diagrams illustrating a weak programming controller and a regulator incorporated in an eighth embodiment of the invention; and
FIGS. 29A and 29B are views showing changes in gate voltage Vg in weak programming performed in the eighth embodiment of the invention.